1988 microchip technology inc. preliminary ds21113d-page 1 features 2.7v to 3.6v supply read access time?00 ns cmos technology for low power dissipation - 8 ma active - 50 m a cmos standby current byte write time? ms data retention >200 years high endurance - minimum 100,000 erase/write cycles automatic write operation - internal control timer - auto-clear before write operation - on-chip address and data latches data polling ready/busy chip clear operation enhanced data protection -v cc detector - pulse filter - write inhibit electronic signature for device identi?ation organized 8kx8 jedec standard pinout - 28-pin dual-in-line package - 32-pin chip carrier (leadless or plastic) available for extended temperature ranges: - commercial: 0?c to +70?c - industrial: -40?c to +85?c description the microchip technology inc. 28lv64a is a cmos 64k non-vol- atile electrically erasable prom organized as 8k words by 8 bits. the 28lv64a is accessed like a static ram for the read or write cycles without the need of external components. during a ?yte write? the address and data are latched internally, freeing the microprocessor address and data bus for other operations. fol- lowing the initiation of write cycle, the device will go to a busy state and automatically clear and write the latched data using an inter- nal control timer. to determine when the write cycle is complete, the user has a choice of monitoring the ready/busy output or using data polling. the ready/busy pin is an open drain output, which allows easy con?uration in ?ired-or systems. alterna- tively, data polling allows the user to read the location last written to when the write operation is complete. cmos design and pro- cessing enables this part to be used in systems where reduced power consumption and reliability are required. a complete family of packages is offered to provide the utmost ?xibility in applica- tions. package types block diagram ?pin 1 indicator on plcc on top of package ?1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rdy/bsy a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v vcc we nc a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 ss a6 a5 a4 a3 a2 a1 a0 nc i/o0 a8 a9 a11 nc oe a10 ce i/o7 i/o6 a7 a12 rdy/bsy nu vcc we nc i/o1 i/o2 vss nu i/o3 i/o4 i/o5 14 15 16 17 18 19 20 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 dip/soic plcc 64k bit cell matrix y gating input/output buffers data poll data protection circuitry chip enable/ output enable control logic auto erase/write timing program voltage generation y decoder x decoder l a t c h e s a0 a12 i i i i i i i i i i i vcc vss ce oe we rdy/ busy i/o0...................i/o7 28lv64a 64k (8k x 8) low voltage cmos eeprom
28lv64a ds21113d-page 2 preliminary 1988 microchip technology inc. 1.0 electrical characteristics maximum ratings* vcc and input voltages w.r.t. v ss ...... -0.6v to + 6.25v voltage on oe w.r.t. v ss ...................... -0.6v to +13.5v voltage on a9 w.r.t. v ss ....................... -0.6v to +13.5v output voltage w.r.t. v ss .................-0.6v to vcc+0.6v storage temperature .......................... -65?c to +150?c ambient temp. with power applied......-55 c to +125 c *notice: stresses above those listed under ?aximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin fuction table name function a0 - a12 address inputs ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs rdy/busy ready/busy v cc + power supply v ss ground nc no connect; no internal connection nu not used; no external connection is allowed table 1-2: read/write operation dc characteristics v cc = 2.7 to 3.6v commercial (c): tamb = 0 c to 70 c industrial (i): tamb = -40 c to 85 c parameter status symbol min max units conditions input voltages logic ? logic ? v ih v il 2.0 0.6 v v input leakage i li 5 ? v in = 0v to v cc +1 input capacitance c in 6 pf vin = 0v; tamb = 25 c; f = 1 mhz (note 1) output voltages logic ? logic ? v oh v ol 2.0 0.3 v v i oh = -100? i ol = 1.0 ma i0 l = 2.0 ma for rdy/busy output leakage i lo 5 ? v out = 0v to v cc +0.1v output capacitance c out ?2pfv out = 0v; tamb = 25 c; f = 1 mhz (note 1) power supply current, activity ttl input i cc 8 ma f = 5 mhz (note 2) i o = oma v cc = 3.3 ce = v il power supply current, standby ttl input ttl input cmos input i cc ( s ) ttl i cc ( s ) ttl i cc ( s ) cmos ? 3 100 ma ma ? ce = v ih (0 c to 70 c ) ce = v ih (-40 c to 85 c ) ce = v cc -3.0 to v cc +1 oe = we = v cc all other inputs equal v cc or v ss note 1: not 100% tested. 2: ac power supply current above 5 mhz: 2 ma/mhz.
1988 microchip technology inc. preliminary ds21113d-page 3 28lv64a table 1-3: read operation ac characteristics figure 1-1: read waveforms ac testing waveform: output load: input rise and fall times: ambient temperature: v ih = 2.0v; v il = 0.6v; v oh = v ol = v cc /2 1 ttl load + 100 pf 20 ns commercial (c): tamb = 0 c to +70 c industrial (i) : tamb = -40 c to +85 c parameter sym 28lv64-30 units conditions min max address to output delay t acc 300 ns oe = ce = v il ce to output delay t ce 300 ns oe = v il oe to output delay t oe 150 ns ce = v il ce or oe high to output float t off 060ns (note 1) output hold from address, ce or oe , whichever occurs first. t oh 0 ns (note 1) endurance 10m cycles 25?, vcc = 5.0v, block mode (note 2) note 1: not 100% tested. 2: this parameter is not tested but guaranteed by characterization. for endurance estimates in a speci? application, please consult the total endurance model which can be obtained on our bbs or website. address ce v ih v il v ih v il v ih v il oe data we v oh v ol v ih v il address valid high z valid output t acc (1) t off is specified for oe or ce , whichever occurs first (2) oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce (3) this parameter is sampled and is not 100% tested high z t oh t off(1,3) notes: t oe(2) t ce(2)
28lv64a ds21113d-page 4 preliminary 1988 microchip technology inc. table 1-4: byte write ac characteristics figure 1-2: programming waveforms ac testing waveform: output load: input rise/fall times: ambient temperature: v ih = 2.0v; v il = 0.6v; v oh = v ol = v cc /2 1 ttl load + 100 pf 20 ns commercial (c): tamb = 0 c to +70 c industrial (i) : tamb = -40 c to +85 c parameter sym min max units remarks address set-up time t as 10 ns address hold time t ah 100 ns data set-up time t ds 120 ns data hold time t dh 10 ns write pulse width t wpl 150 ns (note 1) oe hold time t oeh 10 ns oe set-up time t oes 10 ns data valid time t dv 1000 ns (note 2) time to device busy t db 50 ns write cycle time (28lv64a) t wc 3 ms 1.5 ms typical note 1: a write cycle can be initiated be ce or we going low, whichever occurs last. the data is latched on the positive edge of ce or we , whichever occurs ?st. 2: data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until t dh after the positive edge of we or ce , whichever occurs first. v ih v il v ih v ih v il v oh v ol v ih v il v il twc t db t oeh t oes t dh t ds t wpl t ah t as t dv busy ready rdy/busy oe data in address ce , we
1988 microchip technology inc. preliminary ds21113d-page 5 28lv64a figure 1-3: d a t a polling waveforms figure 1-4: chip clear waveforms table 1-5: supplementary control mode ce oe we a i v cc i/o i chip clear v il v h xv cc extra row read v il v il v ih a9 = v h v cc data out extra row write v ih a9 = v h v cc data in note: v h = 12.0v ?0.5v address valid last written address valid t acc t ce t wpl t wph t dv t wc t oe true data out data in valid v ih v il data oe we ce address i/o7 out v ih v il v ih v il v ih v il v ih v il v h v ih ce oe we t s t h t w t s = = 1? t h = 10ms t w v ih v il v ih v il = 12.0v ?.5v v h
28lv64a ds21113d-page 6 preliminary 1988 microchip technology inc. 2.0 device operation the microchip technology inc. 28lv64a has four basic modes of operation?ead, standby, write inhibit, and byte write?s outlined in the following table. 2.1 read mode the 28lv64a has two control functions, both of which must be logically satis?d in order to obtain data at the outputs. chip enable (ce ) is the power control and should be used for device selection. output enable (oe ) is the output control and is used to gate data to the output pins independent of device selection. assuming that addresses are stable, address access time (t acc ) is equal to the delay from ce to output (tce ). data is available at the output t oe after the fall- ing edge of oe , assuming that ce has been low and addresses have been stable for at least t acc -t oe . 2.2 standb y mode the 28lv64a is placed in the standby mode by apply- ing a high signal to the ce input. when in the standby mode, the outputs are in a high impedance state, inde- pendent of the oe input. 2.3 data pr otection in order to ensure data integrity, especially during criti- cal power-up and power-down transitions, the follow- ing enhanced data protection circuits are incorporated: first, an internal v cc detect (2.0 volts typical) will inhibit the initiation of non-volatile programming opera- tion when v cc is less than the v cc detect circuit trip. second, holding we or ce high or oe low, inhibits a write cycle during power-on and power-off (v cc ). operation mode read standby write inhibit write inhibit write inhibit byte write byte clear ce l h h x x l oe l x x l x h we h x x x h l i/o d out high z high z high z high z d in automatic before each "write" rdy/busy (1) h h h h h l note: (1) open drain output. 2.4 write mode the 28lv64a has a write cycle similar to that of a static ram. the write cycle is completely self-timed and initiated by a low going pulse on the we pin. on the falling edge of we , the address information is latched. on rising edge, the data and the control pins (ce and oe ) are latched. the ready/busy pin goes to a logic low level indicating that the 28lv64a is in a write cycle which signals the microprocessor host that the system bus is free for other activity. when ready/busy goes back to a high, the 28lv64a has completed writing and is ready to accept another cycle. 2.5 data p olling the 28lv64a features data polling to signal the com- pletion of a byte write cycle. during a write cycle, an attempted read of the last byte written results in the data complement of i/o7 (i/o0 to i/o6 can not be determined). after completion of the write cycle, true data is available. data polling allows a simple read/compare operation to determine the status of the chip eliminating the need for external hardware. 2.6 electr onic signature f or de vice identi cation an extra row of 32 bytes of eeprom memory is avail- able to the user for device identi?ation. by raising a9 to 12v 0.5v and using address locations 1feo to 1fff, the additional bytes can be written to or read from in the same manner as the regular memory array. 2.7 chip clear all data may be cleared to 1's in a chip clear cycle by raising oe to 12 volts and bringing the we and ce low. this procedure clears all data, except for the extra row.
28lv64a 28l v64a pr oduct identi cation system to order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed sales of?es. package: l = plastic leaded chip carrier (plcc) p = plastic dip so = plastic small outline ic temperature blank = 0? to +70? range: i = -40 c to +85 c access time: 20 = 200 ns 30 - 300 ns shipping: blank = tube t = tape and reel ? and ?o option: blank = twc = 1ms f = twc = 200? device: 24lv64a 8k x 8 cmos eeprom 28lv64a f t ? 20 i /p 1988 microchip technology inc. ds21113d-page 7
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8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.
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